// this module is consist of a pc register 
// and a adder to calculate pc+4
module PCreg(
    input clk, rst,
    input PCwait,       //keep the PC value when pipeline stall
    input [31:0] PCin,
    output reg [31:0] PCout,
    output wire [31:0] PCout4
);
always@(posedge clk or negedge rst)begin
    if(!rst) PCout <= 32'b0;
    else if(PCwait==1) PCout <= PCout;
    else PCout <= PCin;
end

assign PCout4 = PCout + 32'd4;

endmodule